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+ | == RS-latch == | ||
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An RS-latch is a circuit that stores which of its inputs was last "on". It has typically two inputs: input ''reset'' storing value "0" and input ''set'' storing value "1", hence the name. It can have multiple outputs (possibly inverted), which typically differ mostly in their behavior when multiple inputs are "on" at the same time. Usually, it is considered illegal to set more than one input to "on", but sometimes this is used deliberately (e.g. when constructing an [[Edge-Triggered RS-Latch]]). | An RS-latch is a circuit that stores which of its inputs was last "on". It has typically two inputs: input ''reset'' storing value "0" and input ''set'' storing value "1", hence the name. It can have multiple outputs (possibly inverted), which typically differ mostly in their behavior when multiple inputs are "on" at the same time. Usually, it is considered illegal to set more than one input to "on", but sometimes this is used deliberately (e.g. when constructing an [[Edge-Triggered RS-Latch]]). | ||
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* Output2: Stored value (second value if in illegal state) | * Output2: Stored value (second value if in illegal state) | ||
− | === | + | === Using Logic Select Units === |
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[[File:RS-Latch Using Select Units.png|thumb|An RS-Latch implemented using two Logic Select Units and two Logic Memory units]] | [[File:RS-Latch Using Select Units.png|thumb|An RS-Latch implemented using two Logic Select Units and two Logic Memory units]] |